Transistor scaling has provided ever-increasing transistor performance and density for the past few decades. For example, scaling of a gate length of a transistor, also known as a channel length of a planar transistor, not only decreases a size of the transistor, but also enhances its on-state current. However, with the decrease of the channel length, short channel effects (SCEs) that significantly increases an off-state current of the transistor become a bottle neck for advancement of scaling of the channel length.
Other techniques, such as applying mechanical strain to the channel region are considered to further the progress of performance enhancement. For example, lattice mismatch between the channel region and embedded source and drain regions causes uniaxial strain applied to the channel region, thereby improving carrier mobility of the channel region. Recently, non-planar transistors such as FinFET are shown to be promising in reducing the off-state current by limiting a body thickness of the transistor, thereby breaking through the bottle neck that hinders the scaling roadmap. Planar transistors formed using an ultra thin body semiconductor on insulator (UTB SOI) substrate are also shown to be a viable option.